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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. AD10265 features dual, 65 msps minimum sample rate channel-channel matching, 0.1% gain error channel-channel isolation, >80 db ac-coupled signal conditioning included selectable bipolar input voltage range ( 0.5 v, 1.0 v, 2.0 v) gain flatness up to nyquist: < 0.5 db 80 db spurious-free dynamic range twos complement output format 3.3 v or 5 v cmos-compatible output levels 1.05 w per channel industrial and military grade applications phased array receivers communications receivers flir processing secure communications gps anti-jamming receivers multichannel, multimode receivers functional block diagram d11b (msb) d10b d9b d8b d7b d0b (lsb) d1b d2b d3b d4b d5b d6b d9a d10a d11a (msb) (lsb) d0a d1a d2a d3a d4a d5a d6a d7a d8a encodea 5 7 12 a in b3 encodeb encodeb timing encodea 9 ad9631 ad9632 ain ain a in a2 a in a1 a in a3 12 ad6640 output buffering AD10265 a in b2 a in b1 output buffering timing ad9631 ad9632 ain ain ad6640 dual channel, 12-bit, 65 msps a/d converter with analog input signal conditioning a product description the AD10265 is a full channel adc solution with on-module signal conditioning for improved dynamic performance and fully matched channel-to-channel performance. the module includes two wide dynamic range ad6640 adcs. each ad6640 has an ad9631/ad9632 ac-coupled amplifier front end. the ad6640s have on-chip track-and-hold circuitry, and utilize an innovative multipass architecture, to achieve 12-bit, 65 msps performance. the AD10265 uses innovative high-density circuit design and laser-trimmed thin-film resistor networks to achieve exceptional matching and performance while still main- taining excellent isolation, and providing for significant board area savings. the AD10265 operates with 5.0 v for the analog signal conditioning with a separate +3.3 v supply for the analog-to- digital conversion. each channel is completely independent allowing operation with independent encode and analog inputs. the AD10265 also offers the user a choice of analog input signal ranges to further minimize additional external signal conditioning, while still remaining general-purpose. the AD10265 is packaged in a 68-lead ceramic gull wing pack- age, footprint compatible with the earlier generation ad10242 (12-bit, 40 msps). manufacturing is done on analog devices mil-38534 qualified manufacturers line (qml) and com- ponents are available up to class-t (?5 c to +125 c). the ad6640 internal components are manufactured on analog devices?high-speed complementary bipolar process (xfcb). product highlights 1. guaranteed sample rate of 65 msps. 2. input amplitude options, user configurable. 3. input signal conditioning included; both channels matched for gain. 4. fully tested/characterized performance for full channel. 5. footprint compatible family; 68-lead lccc. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001
rev. a C2C AD10265?pecifications electrical characteristics (av cc = +5 v; av ee = ?.0 v; dv cc = +3.3 v; applies to each adc unless otherwise noted.) test mil AD10265az parameter temp level subgroup min typ max unit resolution 12 bits accuracy no missing codes full iv 12 guaranteed offset error full iv 2, 3 ?0 +3.5 +10 mv gain error 1 25 c i 1 ?.5 0.5 +1.5 % fs full vi 2, 3 ?.5 0.8 +2.5 % fs gain error channel match full v 0.2 % pass band ripple to nyquist full iv 12 0.2 0.5 db analog input (a in ) input voltage range a in 1 full v 0.5 v a in 2 full v 1.0 v a in 3 full v 2v input resistance a in 1 full iv 12 99 100 101 ? a in 2 full iv 12 198 200 202 ? a in 3 full iv 12 396 400 404 ? input capacitance 2 25 c iv 12 0 4.0 7.0 pf analog input bandwidth high 3 25 c v 160 mhz analog input bandwidth low 3 25 c v 50 khz encode input 4, 5 logic compatibility iv ttl/cmos logic ??voltage full iv 2.0 5.0 v logic ??voltage full iv 0 0.8 v logic ??current (v inh = 5 v) full iv 500 650 800 a logic ??current (v inl = 0 v) full iv ?00 ?20 ?00 a input capacitance 25 c iv 12 4.5 7.0 pf switching performance maximum conversion rate 6 full vi 4, 5, 6 65 msps minimum conversion rate 6 full iv 12 6.5 msps aperture delay (t a )25 c v 400 ps aperture delay matching 25 cv 2.0 ns aperture uncertainty (jitter) 25 c v 0.3 ps rms encode pulsewidth high 25 c iv 12 6.5 ns encode pulsewidth low 25 c iv 12 6.5 ns output delay (t od ) full iv 12 7.0 9.0 12.5 ns snr 7 analog input @ 1.24 mhz 25 ci 4 62 66 db full ii 5, 6 60.5 66 db @ 17 mhz 25 ci 4 61 65 db full ii 5, 6 60 65 db @ 32 mhz 25 ci 4 61 63 db full ii 5, 6 59.5 62 db sinad 8 analog input @ 1.24 mhz 25 ci 4 61 65 db full ii 5, 6 60 64 db @ 17 mhz 25 ci 4 61 64 db full ii 5, 6 59.5 63 db @ 32 mhz 25 ci 4 61 62 db full ii 5, 6 59 62 db
test mil AD10265az parameter temp level subgroup min typ max unit spurious-free dynamic range 9 analog input @ 1.24 mhz 25 c i 4 75 80 dbfs full ii 5, 6 74 80 dbfs @ 17 mhz 25 c i 4 71 80 dbfs full ii 5, 6 70 79 dbfs @ 32 mhz 25 c v 79 dbfs full v 79 dbfs two-tone imd rejection 10 f1, f2 @ ? dbfs full v 4, 5, 6 66 77 dbc channel- to-channel isolation 11 25 civ12 80 db linearity differential nonlinearity (encode = 20 mhz) 25 c iv 12 ?.0 0.5 +1.5 lsb integral nonlinearity (encode = 20 mhz) full v 1.25 lsb digital outputs logic compatibility cmos logic ??voltage full i 1, 2, 3 2.8 dv cc ?0.2 v logic ??voltage full i 1, 2, 3 0.2 0.5 v output coding two? complement power supply av cc supply voltage full v +5.0 v i (av cc ) current full v 336 ma av ee supply voltage full v ?.0 v i (av ee ) current full v 66 ma dv cc supply voltage full v +3.3 v i (dv cc ) current full v 20 ma i cc (total) supply current full i 1, 2, 3 422 520 ma power dissipation (total) full i 1, 2, 3 2.1 2.4 w power supply rejection ratio (psrr) full iv 12 0.01 0.02 % fsr/% v s notes 1 gain tests are performed on a in 1 over specified input voltage range. 2 input capacitance specifications show only ceramic package capacitance. 3 full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by fft analysis) is reduced by 3 db. 4 encode driven by single-ended source; encode bypassed to ground through 0.01 f capacitor. 5 encode may also be driven differentially in conjunction with encode ; see ?ncoding the AD10265?for details. 6 minimum and maximum conversion rates allow for variation in encode duty cycle of 50% 5%. 7 analog input signal power at ? dbfs; signal-to-noise ratio (snr) is the ratio of signal level to total noise (first 5 harmonic s removed). encode = 65 msps. 8 analog input signal power at ? dbfs; signal-to-noise and distortion (sinad) is the ratio of signal level to total noise + harm onics. encode = 65 msps. 9 analog input signal equal ? dbfs; sfdr is ratio of converter full scale to worst spur. 10 both input tones at ? dbfs; two-tone intermodulation distortion (imd) rejection is the ratio of either tone to the worst third order intermod product. f1 = 17.0 mhz 100 khz, f2 = 18.0 mhz 100 khz. 11 channel-to-channel isolation tested with a channel/50 ohm terminated AD10265 C3C rev. a
AD10265 C4C rev. a absolute maximum ratings 1 parameter min max unit electrical v cc voltage 0 +7 v v ee voltage ? 0 v analog input voltage v ee v cc v analog input current ?0 +10 ma digital input voltage (encode) 0 av cc v encode, encode differential voltage 4 v digital output current ?0 +10 ma environmental 2 operating temperature (case) ?5 +125 c maximum junction temperature 175 c lead temperature (soldering, 10 sec) 300 c storage temperature range (ambient) ?5 +150 c notes 1 absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability is not necessarily implied. exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 typical thermal impedances for ??package: jc = 11 c/w; ja = 30 c/w. table i. output coding msb lsb base 10 input 0111111111111 2047 +fs 0000000000001 +1 0000000000000 0 0.0 v 1111111111111 ? 1000000000000 2048 ?s explanation of test levels test level i. 100% production tested. ii. 100% production tested at 25 c, and sample tested at specified temperatures. ac testing done on sample basis. iii. sample tested only. iv. para meter is guaranteed by design and characteriza- tion testing. v. parameter is a typical value only. vi. all devices are 100% production tested at 25 c; sample tested at temperature extremes. ordering guide m odel temperature range package description package option AD10265az ?5 c to +85 c (case) 68-lead ceramic leaded chip carrier es-68c AD10265/pcb +25 c evaluation board with AD10265az 5962-9865901 hxa ?5 c to +125 c (case) 68-lead ceramic leaded chip carrier es-68c 5962r0151901 txa ?5 c to +125 c (case) 68-lead ceramic leaded chip carrier es-68c caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD10265 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
rev. a AD10265 C5C pin function descriptions pin no. name function 1 shield internal ground shield between channels. 2, 5, 9?1, 26, 27 gnda a channel ground. a and b grounds should be connected as close to the device as possible. 3, 4, 12, 15, 16, nc no connect. pins 15 and 16 are internal test pins: it is recommended to connect 34, 35, 55?7 them to gnd. 6a in a1 analog input for a side adc (nominally 0.5 v). 7a in a2 analog input for a side adc (nominally 1.0 v). 8a in a3 analog input for a side adc (nominally 2.0 v). 13 av ee analog negative supply voltage (nominally ?.0 v). for a side adc. 14 av cc analog positive supply voltage (nominally +5.0 v). for a side adc. 17?5, 31?3 d0a?11a digital outputs for adc a. d0 (lsb). 28 encodea encode is complement of encode. 29 encodea data conversion initiated on rising edge of encode input. 30 dv cc digital positive supply voltage (nominally 3.3 v) for a side adc. 36?2, 45?9 d0b?11b digital outputs for adc b. d0 (lsb). 43, 44, 53, 54, gndb b channel ground. a and b grounds should be connected as close to the device 58?1, 65, 68 as possible. 50 dv cc digital positive supply voltage (nominally 3.3 v) for b side adc. 51 encodeb data conversion initiated on rising edge of encode input. 52 encodeb encode is complement of encode. 62 a in b1 analog input for b side adc (nominally 0.5 v). 63 a in b2 analog input for b side adc (nominally 1.0 v). 64 a in b3 analog input for b side adc (nominally 2.0 v). 66 av cc analog positive supply voltage (nominally +5.0 v). for b side adc. 67 av ee analog negative supply voltage (nominally ?.0 v). for b side adc. pin configuration 68-lead ceramic leaded chip carrier 10 11 12 13 14 15 16 17 18 19 20 22 23 24 25 26 21 27 43 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 961 8 7 6 5 68 67 66 65 64 63 62 4321 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 top view (not to scale) gndb gndb gndb nc nc nc gndb gndb encodeb encodeb dv cc d11b (msb) d10b d9b d8b d7b gndb gnda dv cc d9a d10a (msb) d11a encodea encodea nc nc d1b d2b d3b d4b d5b d6b gndb (lsb) d0b gnda gnda nc av ee av cc nc nc (lsb) d0a d1a d2a d3a d4a d5a d6a d7a d8a gnda nc = no connect gnda gndb gnda a in a1 gnda nc nc av ee a in b3 av cc gndb a in a3 a in a2 gndb a in b1 a in b2 shield AD10265 pin 1
AD10265 C6C rev. a output propagation delay the delay between the 50% point of the rising edge of encode command and the time when all output data bits are within valid logic levels. power supply rejection ratio the ratio of a change in input offset voltage to a change in power supply voltage. signal-to-noise-and-distortion (sinad) the ratio of the rms signal amplitude (set at 1 db below full scale) to the rms value of the sum of all other spectral compo- nents, including harmonics but excluding dc. signal-to-noise ratio (without harmonics) the ratio of the rms signal amplitude (set at 1 db below full scale) to the rms value of the sum of all other spectral compo- nents, excluding the first five harmonics and dc. spurious-free dynamic range the ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. the peak spurious compo- nent may or may not be a harmonic. may be reported in dbc (i.e., degrades as signal level is lowered) or in dbfs (always related back to converter full scale). two-tone intermodulation distortion rejection the ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dbc. two-tone sfdr the ratio of the rms value of either input tone to the rms value of the peak spurious component. the peak spurious component may or may not be an imd product. may be reported in dbc (i.e., degrades as signal level is lowered) or in dbfs (always related back to converter full scale). definition of specifications analog bandwidth the analog input frequency at which the spectral power of the fundamental frequency (as determined by the fft analysis) is reduced by 3 db. aperture delay the delay between the 50% point of the rising edge of the encode command and the instant at which the analog input is sampled. aperture uncertainty (jitter) the sample-to-sample variation in aperture delay. differential nonlinearity the deviation of any code from an ideal 1 lsb step. encode pulsewidth/duty cycle pulsewidth high is the minimum amount of time that the encode pulse should be left in logic ??state to achieve rated performance; pulsewidth low is the minimum time encode pulse should be left in low state. at a given clock rate, these specs define an acceptable encode duty cycle. harmonic distortion the ratio of the rms signal amplitude to the rms value of the worst harmonic component. integral nonlinearity the deviation of the transfer function from a reference line measured in fractions of 1 lsb using a ?est straight line determined by a least square curve fit. minimum conversion rate the encode rate at which the snr of the lowest analog signal frequency drops by no more than 3 db below the guaranteed limit. maximum conversion rate the encode rate at which parametric testing is performed.
rev. a AD10265 C7C enc d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1/2 AD10265 shown ttl clock f 10mhz note: all 5v supply pins bypassed to gnd with a 0.1 f capacitor a in a3 a in a2 a in a1 enc 2qo n2rb0qbab2q20 a in encode n n ?2 n + 2 n + 3 n + 4 n + 5 t a t od n + 1 n ?1 n n + 1 n + 2 digital outputs figure 1. timing diagram equivalent circuits a in a3 r4 200 a in a2 a in a1 r3 100 figure 3. analog input stage timing circuits encode av cc av cc r1 17k r2 8k r2 8k r1 17k av cc encode figure 4. encode inputs dv cc v ref dv cc current mirror current mirror d0 d11 figure 5. digital output stage
C8C rev. a AD10265 typical performance characteristics frequency mhz 0 power relative to full scale db 60 100 0 8192 1024 2048 3072 4096 5120 6144 7168 10 50 70 90 30 40 80 20 140 110 130 120 encode = 65.0msps a in = 1.24mhz a in = 1.004dbfs snr = 64.88db sfdr = 78.81dbc tpc 1. single tone @ 1.24 mhz frequency mhz 0 power relative to full scale db 60 100 0 8192 1024 2048 3072 4096 5120 6144 7168 10 50 70 90 30 40 80 20 140 110 130 120 encode = 65.0msps a in = 17mhz a in = 1dbfs snr = 63.83db sfdr = 78.22dbc tpc 2. single tone @ 17 mhz frequency mhz 0 power relative to full scale db 60 100 0 8192 1024 2048 3072 4096 5120 6144 7168 10 50 70 90 30 40 80 20 140 110 130 120 encode = 65.0msps a in = 32mhz a in = 1.021dbfs snr = 64.11db sfdr = 78.14dbc tpc 3. single tone @ 32 mhz frequency mhz 0 power relative to full scale db 60 100 0 8192 1024 2048 3072 4096 5120 6144 7168 10 50 70 90 30 40 80 20 140 110 130 120 encode = 65.0msps a in = 17mhz and 18mhz a in = 7.067dbfs sfdr = 78dbc tpc 4. two-tone fft @ 17 mhz/18 mhz analog frequency mhz 60 1.24 32 17 66 64 63 61 65 62 encode = 65mhz +25 c snr db +125 c 55 c tpc 5. snr vs. a in fundamental dbfs 40 0 70.18 50.18 60.09 80 50 10 a in = 17mhz encode rate 65mhz sfdr dbc 20 30 60 sfdr dbc 70 sfdr 75db sfdr dbfs 39.92 30.07 20.02 10.1 1.099 90 tpc 6. single-tone sfdr (a in @ 17 mhz) vs. power level
rev. a AD10265 C9C analog input frequency mhz 60 0 1.24 17 40 20 encode frequency = 65mhz a in = 1dbfs snr db 30 50 10 32 37 65 80 100 70 80 sfdr dbc snr, worst spur db, dbc 90 tpc 7. snr/harmonics to a in > nyquist msps frequency mhz 2 7 0.02 5 4 3 6 0.06 0.1 0.5 1 0 120 160 60 level dbfs encode rate = 65mhz room temperature 8 9 10 0.04 0.08 0.3 20 140 90 .2,1 <( (
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AD10265 C10C rev. a theory of operation refer to the functional block diagram. the AD10265 em ploys three monolithic adi components per channel (ad9631, ad9632, and ad6640), along with multiple passive resistor networks and decoupling capacitors to fully integrate a com plete 12-bit analog-to-digital converter. the input signal is first passed through a precision laser-trimmed resistor divider, allowing the user to externally select operation with a full-scale signal of 0.5 v, 1.0 v, or 2.0 v by choosing the proper input terminal for the application. since the ad6640 implements a true differential analog input, the ad9631/ad9632 have been configured to provide a differ- ential input for the ad6640 adc through ac-coupling. the ac signal gain of the ad9631/ad9632 can be trimmed to pro vide a constant differential input to the ad6640. this allows the converter to be used in multiple system applications without the need for external gain circuit normally requiring trim. the ad9631/ad9632 were chosen for their superior ac performance and input drive capabilities, which have limited the ability of many amplifiers to drive high-performance adcs. as new amplifiers are developed, pin-compatible improvements are planned to incorporate the latest operational amplifier technol ogy. applying the AD10265 encoding the AD10265 best performance is obtained by driving the encode pins differ- entially. however, the AD10265 is also designed to interface with ttl and cmos logic families. the source used to drive the encode pin(s) must be clean and free from jitter. sources with excessive jitter will limit snr and overall performance. 0.01 f ttl or cmos source encode encode AD10265 figure 6. single-ended ttl/cmos encode the AD10265 encode inputs are connected to a differential input stage (see figure 4 under equivalent circuits). with no input connected to either encode pin, the voltage divider biases the inputs to 1.6 v. for ttl or cmos usage, the en code source should be connected to encode. encode should be decoupled using a low inductance or microwave chip capacitor to ground. if a logic threshold other than the nominal 1.6 v is required, the following equations show how to use an external resistor, rx, to raise or lower the trip point (see figure 4, r1 = 17 k ? , r2 = 8 k ? ). v rr rr rrx r rx 1 52 12 1 2 = ++ x to lower logic threshold. 0.01 f encode source encode encode AD10265 r x v 1 5v r1 r2 figure 7. lower threshold for encode v r r rrx rrx 1 52 2 1 1 = + + to raise logic threshold. 0.01 f encode source encode encode AD10265 r x v 1 5v r1 r2 av cc figure 8. raise logic threshold for encode while the single-ended encode will work well for many applica- tions, driving the encode differentially will provide increased performance. depending on circuit layout and system noise, a 1 db to 3 db improvement in snr can be realized. it is recommended that differential ttl logic be used, however, because most ttl families that support complementary outputs are not delay or slew rate matched. instead, it is recom mended that the encode signal be ac-coupled into the encode and encode pins. the simplest option is shown below. the low jitter ttl signal is coupled with a limiting resistor, typically 100 ? , to the primary side of an rf transformer (these transformers are inexpen sive and readily available; part number in figure 9 is from mini- circuits). the secondary side is connected to the encode and encode pins of the converter. since both encode in puts are self-biased, no additional components are required. ttl encode encode AD10265 100 t1 1t figure 9. ttl sourcedifferential encode a clean sine wave may be substituted for a ttl clock. in this case, the matching network is shown below. select a transformer ratio to match source and load impedances. the input imped ance of the AD10265 encode is approximately 11 k ? differentially. therefore r, shown in figure 10, may be any value that is convenient for available drive power. encode encode AD10265 r t1 1t sine source figure 10. sine sourcedifferential encode
rev. a AD10265 C11C if a low jitter ecl clock is available, another option is to ac- couple a differential ecl signal to the encode input pins as shown below. the capacitors shown here should be chip capacitors, but do not need to be of the low inductance variety. encode encode AD10265 ecl gate 0.1 f 0.1 f v s 510 510 figure 11. differential ecl for encode as a final alternative, the ecl gate may be replaced by an ecl comparator. the input to the comparator could then be a logic signal or a sine signal. encode encode AD10265 0.1 f 0.1 f v s 50 ad96687 (1/2) 510 510 figure 12. ecl comparator for encode using the flexible input the AD10265 has been designed with the user s ease of opera tion in mind. multiple input configurations have been included on board to allow the user a choice of input signal levels and input impedance. while the standard inputs are 0.5 v, 1.0 v, and 2.0 v, the user can select the input impedance of the ad 10265 on any input by using the other inputs as alternate locations for gnd or an external resistor. the following chart summa rizes the impedance options available at each input location: a in 1 = 100 ? when a in 2 and a in 3 are open. a in 1 = 75 ? when a in 3 is shorted to gnd. a in 1 = 50 ? when a in 2 is shorted to gnd. a in 2 = 200 ? when a in 3 is open. a in 2 = 100 ? when a in 3 is shorted to gnd. a in 2 = 75 ? when a in 2 to a in 3 has an external resistor of a in 2 = 300 ? , with a in 3 shorted to gnd. a in 2 = 50 ? when a in 2 to a in 3 has an external resistor of a in 2 = 100 ? , with a in 3 shorted to gnd. a in 3 = 400 ? . a in 3 = 100 ? when a in 3 has an external resistor of 133 ? to gnd. a in 3 = 75 ? when a in 3 has an external resistor of 92 ? to gnd. a in 3 = 50 ? when a in 3 has an external resistor of 57 ? to gnd. grounding and decoupling analog and digital grounding proper grounding is essential in any high speed, high resolution system. multilayer printed circuit boards (pcbs) are recom- mended to provide optimal grounding and power schemes. the use of ground and power planes offers distinct advantages: 1. the minimization of the loop area encompassed by a signal and its return path. 2. the minimization of the impedance associated with ground and power paths. 3. the inherent distributed capacitor formed by the power plane, pcb insulation, and ground plane. these characteristics result in both a reduction of electro magnetic interference (emi) and an overall improvement in perfor mance. it is important to design a layout that prevents noise from cou pling to the input signal. digital signals should not be run in parallel with input signal traces and should be routed away from the input circuitry. the AD10265 does not distinguish between analog and digital ground pins as the AD10265 should always be treated as an analog component. all ground pins should be connected together directly under the AD10265. the pcb should have a ground plane covering all unused portions of the component side of the board to provide a low impedance path and manage the power and ground currents. the ground plane should be removed from the area near the input pins to reduce stray capacitance. layout information the schematic of the evaluation board (figure 13) represents a typical implementation of the AD10265. the pinout of the AD10265 is very straightforward and facilitates ease of use and the implementation of high frequency/high resolution design practices. it is recommended that high quality ceramic chip capacitors be used to decouple each supply pin to ground directly at the device. all capacitors can be standard high quality ceramic chip capacitors. care should be taken when placing the digital output runs. because the digital outputs have such a high slew rate, the capacitive loading on the digital outputs should be minimized. circuit traces for the digital outputs should be kept short and connect directly to the receiving gate. internal circuitry buffers the outputs of the ad6640 adc through a resistor network to eliminate the need to externally isolate the device from the receiving gate.
AD10265 C12C rev. a u1 AD10265 agnda dgnda dgndb l10 47 l7 47 c22 10 f 5.2vaa c53 10 f +5vaa agndb drbout c61 0.1 f agndb +3.3vdb c58 10 f l6 47 c64 0.1 f dgndb l9 47 c59 10 f 5.2vab c57 0.1 f agnda agnda agndb c52 10 f agndb l8 47 47 at 100mhz c63 0.1 f l11 47 c62 10 f dgnda dgnda +3.3vda 47 at 100mhz 47 at 100mhz agnda 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 gndb gndb gndb nc nc nc gndb gndb encbb encb dv cc d11b(msb) d10b d9b d8b d7b gndb encbb encb dut 3.3vdb d13b(msb) d12b d11b d10b d9b 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 agnda a in a3 a in a2 a in a1 agnda nc nc agnda shield agndb av ee av ee gndb ainb3 ainb2 ainb1 gndb +5vab a in b3 a in b2 a in b1 a in a3 a in a2 a in a1 agnda agnda nc av ee av ee nc nc d0a(lsb) d1a d2a d3a d4a d5a d6a d7a d8a dgnda 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 dgnda encab enca dv cc d9a d10a d11a(msb) nc nc d0b(lsb) d1b d2b d3b d4b d5b d6b dgndb 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 encab enca dut 3.3vda d11a d12a d13a d0b d1b d2b d3b d4b d5b d6b d7b d8b av ee d0a d1a d2a d3a d4a d5a d6a d7a d8a d9a d10a +5vab a in b3 j1 agndb a in b2 j2 agndb a in b1 j22 agndb a in a3 j7 agnda a in a2 j8 agnda a in a1 j20 agnda dut 3.3vdb c26 0.1 f dgndb dgndb spare gate u2:c dut 3.3vda c27 0.1 f dgnda dgnda spare gate u4:c 10 9 10 9 88 74lcx00m 74lcx00m u2:a 1 2 jp5 3 u2:d 13 12 11 u2:b 4 5 6 jp1 buflatb latchb jp3 draout clklatcha1 jp4 u4:a 1 2 3 u4:d 12 11 u4:b 4 5 6 13 74lcx00m 74lcx00m 74lcx00m 74lcx00m 74lcx00m 74lcx00m jp2 buflata clklatchb2 clklatchb1 drbout clklatcha2 jp6 latcha nc = no connect figure 13a. evaluation board schematic
rev. a AD10265 C13C j18 agnda r83 51 c40 0.1 f agnda j6 agnda r82 51 c42 0.1 f agnda jp8 jp11 open encodea e ncodea nc = no connect v cc q q v ee nc d d v bb u7 mc10ep16d agnda 1 2 3 4 8 7 6 5 out nr in sd u6 agnda 2 6 1 8 err 3 +5vaa c45 100pf gnd agnda jp7 r140 33k 4 +5vaa c41 0.47 f agnda r89 100 agnda r94 100 c49 0.1 f c44 0.1 f encab enca adp3330 j17 agndb r79 51 c39 0.1 f agndb j16 agndb r76 51 c37 0.1 f agndb jp12 open encodeb e ncodeb nc = no connect v cc q q v ee nc d d v bb u9 mc10ep16d agndb 1 2 3 4 8 7 6 5 out nr in sd u8 agndb 2 6 1 8 err 3 +5vaa c43 100pf gnd agndb jp9 r141 33k 4 +5vaa c38 0.47 f agndb r95 100 agndb r97 100 c46 0.1 f c48 0.1 f encb encbb adp3330 jp10 figure 13b. evaluation board schematic
AD10265 C14C rev. a nc d d v bb v cc q q v ee 1 2 3 4 8 7 6 5 dut_3.3vda r92 33k u10 mc10ep16d dut_3.3vda dgnda dgnda c47 0.1 f r90 100 r91 100 dgnda d0 d0 d1 d1 v cc q q gnd 1 2 3 4 8 7 6 5 dut_3.3vda dgnda dgnda c51 0.1 f u11 mc100ept23 clklatcha1 clklatcha2 nc d d v bb v cc q q v ee 1 2 3 4 8 7 6 5 dut_3.3vdb r93 33k u12 mc10ep16d dut_3.3vdb dgndb dgndb c54 0.1 f r138 100 r96 100 dgndb d0 d0 d1 d1 v cc q q gnd 1 2 3 4 8 7 6 5 dut_3.3vdb dgndb dgndb c65 0.1 f u13 mc100ept23 clklatchb1 clklatchb2 jp8 jp7 jp10 jp9 figure 13c. evaluation board schematic
rev. a AD10265 C15C dut 3.3vda c20 0.1 f c15 0.1 f c14 0.1 f c13 0.1 f dgnda e1 e2 e3 e4 e5 e6 e7 e8 e9 +5vaa +5vab +3.3vda +3.3vdb 5.2vab agndb agnda dgnda dgndb 5.2vaa e10 u21 25 24 26 27 42 31 7 16 29 30 32 33 23 22 20 19 35 36 48 17 16 14 13 1 37 38 40 12 11 41 43 44 9 8 6 5 46 47 28 3 2 21 15 34 39 18 4 cp2 oe2 i15 i14 i10 i4 i0 45 i11 i12 i8 i13 i7 i6 i5 i1 i3 i2 gnd i9 o10 o7 o3 o0 gnd o6 o5 o4 o2 o1 gnd gnd gnd o9 o11 o12 o13 o14 o15 vcc vcc vcc vcc o8 cp1 oe1 gnd gnd gnd 74lcx163743mtd (lsb) d0a d1a d2a d3a d4a d5a d12a (msb) d13a d11a d10a d9a d8a d7a d6a r99 0 dgnda r100 0 r98 51 dgnda dut 3.3vda 21 22 23 24 25 26 27 28 29 30 31 32 35 36 37 38 39 40 33 34 21 22 23 24 25 26 27 28 29 30 31 32 35 36 37 38 39 40 33 34 20 19 18 17 16 15 14 13 12 11 10 9 6 5 4 3 2 1 8 7 20 19 18 17 16 15 14 13 12 11 10 9 6 5 4 3 2 1 8 7 r113 100 r105 100 r104 100 r106 100 r117 100 r115 100 r116 100 r114 100 dgnda r108 100 r107 100 r110 100 r111 100 r102 100 r101 100 r109 100 r103 100 j3 r118 51 buflata latcha msb dut 3.3vda c24 0.1 f c23 0.1 f c21 0.1 f c25 0.1 f dgndb u22 25 24 26 27 42 31 7 16 29 30 32 33 23 22 20 19 35 36 48 17 16 14 13 1 37 38 40 12 11 41 43 44 9 8 6 5 46 47 28 3 2 21 15 34 39 18 4 cp2 oe2 i15 i14 i10 i4 i0 45 i11 i12 i8 i13 i7 i6 i5 i1 i3 i2 gnd i9 o10 o7 o3 o0 gnd o6 o5 o4 o2 o1 gnd gnd gnd o9 o11 o12 o13 o14 o15 vcc vcc vcc vcc o8 cp1 oe1 gnd gnd gnd 74lcx163743mtd (lsb) d0b d1b d2b d3b d4b d5b d12b (msb) d13b d11b d10b d9b d8b d7b d6b r124 0 dgndb r123 0 r119 51 dgndb dut 3.3vdb 21 22 23 24 25 26 27 28 29 30 31 32 35 36 37 38 39 40 33 34 21 22 23 24 25 26 27 28 29 30 31 32 35 36 37 38 39 40 33 34 20 19 18 17 16 15 14 13 12 11 10 9 6 5 4 3 2 1 8 7 20 19 18 17 16 15 14 13 12 11 10 9 6 5 4 3 2 1 8 7 r130 100 r129 100 r128 100 r134 100 r112 100 r127 100 r126 100 r125 100 dgndb r133 100 r120 100 r121 100 r122 100 r136 100 r131 100 r132 100 r135 100 j4 r137 51 buflatb latchb msb e162 e163 e164 e165 e166 e171 e172 e177 e179 e181 e186 e187 e207 e209 e211 e213 e215 e217 e219 e221 e227 e229 e231 e233 e159 e160 e161 e167 e168 e169 e170 e178 e180 e182 e183 e191 e192 e193 e208 e210 e212 e214 e216 e218 e220 e222 e228 e230 e232 e234 dgndb agndb e89 e139 e143 e146 e148 e149 e152 e153 e184 e188 e189 e190 e195 e197 e199 e201 e203 e205 e224 e226 e87 e88 e72 e140 e141 e142 e144 e145 e147 e150 e151 e154 e185 e194 e196 e198 e200 e202 e204 e206 e223 e225 dgnda agnda banana jacks for gnds and pwrs lsb lsb figure 13d. evaluation board schematic
AD10265 C16C rev. a 6.20 0.005 0.00 5.50 0.005 0.00 figure 14. evaluation board mechanical layout evaluation board the AD10265 evaluation board (figure 14) is designed to provide optimal performance for evaluation of the AD10265 analog-to-digital converter. the board encompasses everything needed to ensure the highest level of performance for evaluating the AD10265. power to the analog supply pins is connected via banana jacks. the analog supply powers the crystal oscillator, the associated components and amplifiers, and the analog section of the AD10265. the digital outputs of the AD10265 are powered via pin 1 of either j1 or j2 found on the digital interface connector with 3.3 v. contact the factory if additional layout or applica- tions assistance is required.
rev. a AD10265 C17C bill of materials list for AD10265 evaluation board reference manufacturer and component qty designator value description part number name 2 u2, u4 ic, low-voltage quad 2-input nand, soic-14 toshiba/tc74lcx00fn 74lcx00m 2 u21, u22 ic, 16-bit transparent latch with three-state fairchild/74lcx163743mtd 74lcx163743mtd outputs, tssop-48 1 u1 dut, ic 14-bit analog-to-digital converter adi/AD10265az adi/ad10465az 2 u6, u8 ic, voltage regulator 3.3 v, rt-6 analog devices/adp3330art-3, adp3330 3-rlt 10 e1 e10 banana jack, socket johnson components/08-0740-001 banana hole 30 c13 c15, 0.1 f capacitor, 0.1 f, 20%, 12 v dc, 0805 mena/grm40x7r104k025bl cap 0805 c20, c21, c23 c27, c37, c39, c40, c41, c42, c44, c46, c47, c48, c49, c54 c58, c60, c61, c63, c64, c65 2 c38, c41 0.47 f capacitor, 0.47 f, 5%, 12 v dc, 1206 vitramon/vj1206u474mfxmb cap 1206 2 c43, c45 100 pf capacitor, 100 pf, 10%, 12 v dc, 0805 johansen/500r15n101jv4 cap 0805 2 j3, j4 connector, 40-pin header male st. samtec/tsw-120-08-g-d hd40m 6l6 l11 47 h inductor, 47 h @ 100 mhz, 20%, ind2 fair-rite/2743019447 ind2 4 u7, u9, u10, u11 ic, differential receiver, soic-8 motorola/mc10ep16d mc10ep16d 6 c22, c50, c52, c53, c59, c62 10 f capacitor, 10 f, 20%, 16 v dc, 1812pol kemet/t491c106m016a57280 polcap 1812 4 r99, r100, r123, r124 0.0 ? resistor, 0.0 ? , 0805 panasonic/erj-6gey0r00v res2 0805 4 r92, r93, 33,000 ? resistor, 33,000 ? , 5%, 0.10 watt, 0805 panasonic/erj-6geyj333v res2 0805 r140, r141 8 r76, r79, r82, 51 ? resistor, 51 ? , 5%, 0.10 watt, 0805 panasonic/erj-6geyj510v res2 0805, res 0805 r83, r98, r118, r119, r137 40 r89, r90, r91, 100 ? resistor, 100 ? , 5%, 0.10 watt, 0805 panasonic/erj-6geyj101v res2 0805, res 0805 r94, r95, r97, r101 r117, r120 r122, r125 r136, r138 8 j1, j2, j6 j8, connector, sma female st. johnson components/142-0701-201 sma j16 j18, j20, j22 2 u11, u13 ic op amp, soic-8 motorola/mc100ept23 mc100ept23
AD10265 C18C rev. a figure 15. top layer copper figure 16. second layer copper
rev. a AD10265 C19C figure 17. third layer copper figure 18. fourth layer copper
AD10265 C20C rev. a figure 19. fifth layer copper figure 20. bottom layer copper
rev. a AD10265 C21C figure 21. bottom silkscreen figure 22. bottom assembly
AD10265 C22C rev. a outline dimensions dimensions shown in inches and (mm). 68-lead ceramic leaded chip carrier (es-68c) 0.060 (1.52) 0.240 (6.096) top view (pins down) pin 1 10 26 961 60 43 27 44 0.050 (1.27) 0.950 (24.13) sq 0.018 (0.457) 0.800 (20.32) 1.180 (29.97) sq
C23C
c00666C0C6/01(a) printed in u.s.a. C24C

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